1. Field of the Invention
The present invention relates to an LSI design method including a plurality of macro blocks. More particularly, the present invention relates to an LSI design method, which never produces a timing error having influence on an entire specification of an LSI function, after design of a layout and a circuit of detailed portions.
2. Description of the Related Art
A conventional LSI design method including a plurality of macro blocks is described with reference to attached drawings. FIG. 1 is a flowchart showing a flow of the conventional LSI design method.
At first, in an LSI function specification determining step 21, a function specification to be defined as the LSI is determined. Next, the function specification is divided into a plurality of function modules. Then, in a function module designing step 22, all the function modules of the LSI are designed.
Next, in a layout step 23, a mask layout on the entire LSI is performed. Moreover, in a timing analysis step 24, a timing analysis as to whether or not the layout circuit satisfies a desirable timing specification is performed based on the layout result.
As a result of the timing analysis, if the desirable timing is not obtained and a timing error is brought about, the operational flow returns back to any one of the LSI function specification determining step 21, the function module designing step 22 and the layout step 23, on the basis of content of the timing error. Again, the design is tried.
In the above-mentioned conventional LSI design method, the timing analysis 24 between the function modules or a delay analysis can not be performed, unless the layout 23 for the entire LSI is executed after completion of all the function module designs 22. If the timing error occurs at the timing analysis step 24, the operational flow returns back to any one of the LSI function specification determining step 21, the function module designing step 22 and the layout step 23, on the basis of the content of the timing error. Again, the design is tried.
Especially, if the timing error can not be solved only by retrying the layout 23 or the function module design 22 and further the review of the timing of the entire system is required and thereby the LSI function specification determination 21 must be retried, the design must be retried from the original stage, at the final stage of the LSI design. Thus, this results in the large retrial, and also leads to the increase of a design time.
Japanese Laid Open Patent Application (JP-A-Heisei-5-197774) discloses the following method of modifying a circuit. A circuit generator having a high level synthesizer which receives an operational specification and prepares an inner representation based on its specification is provided with an input output interface device, an analysis modification managing device and a synthesis modification executing device. The synthesis modification executing device prepares a floor plan of a circuit based on the input operational specification, and checks it based on a constraint item. If there is a violation, the analysis modification managing device analyzes it, and outputs a modification plan.
Japanese Laid Open Patent Application (JP-A-Heisei 9-153084) discloses the following method of automatically designing LSI. After an input of a net list between function macros, a schematic layout process for the function macro is done based on this net list, and a physical specification of the function macro is determined on the basis of the schematic layout. Then, a logically synthesizing process is done based on the determined physical specification, and the layout is performed on the logic obtained from the logical synthesis, based on the schematic layout of the function macro. Thus, the retrial of the circuit synthesis and the like can be extremely reduced by watching out the layout from a stage of a function design for upper layer in which a gate level is not determined. Hence, it is possible to complete the layout design of LSI, in which a delay time and an area of the LSI are optimal, in a short time.
Japanese Laid Open Patent Application (JP-A-Heisei 10-171857) discloses the following method of designing an integrated circuit. Various modules usable as components of design target are registered as parameterized models. Database is prepared in advance for accumulating therein an instance generation information indicative of a procedure of generating an instance for the various modules and an index calculation information indicative of a manner of calculating a design quality index for each abstract. Then, this database is used to design the orientation of a floor plan. That is, also in a high level of an operational level and an RT level, the design quality indexes of the various modules used for the design are calculated by using the database. Then, they are used to execute the floor plan. In accordance with the execution result, the design quality indexes of a circuit size, a delay time and a consumption power of the design target and the like are calculated to accordingly judge whether or not the change of the design is required (whether or not the design specification is satisfied).
The present invention has been made to solve the above-described problems of the conventional LSI design method. An object of the present invention is to provide an LSI design method of performing a timing analysis at an early stage of LSI design to avoid an occurrence of large retry. Another object of the present invention is to perform a timing analysis on an entire LSI before designing an RT (Register Transfer) level of a function module to avoid the change of the specification, the change of the circuit and the re-layout of the entire LSI resulting from a timing error immediately before the end of the LSI design.
In order to achieve an aspect of the present invention, an LSI design method, includes (a) performing an arrangement wiring on a plurality of macro blocks, (b) performing a timing analysis on the plurality of macro blocks based on the result of the (a) step, and (c) designing an inside portion of each of the plurality of macro blocks based on the result of the (b) step.
In this case, the (b) step includes performing the timing analysis in consideration of a wiring capacitance and a wiring resistor corresponding to the result of the (a) step.
Also in this case, the (c) step includes performing a register transfer level design, a circuit design and a layout design on the inside portions such that the plurality of macro blocks satisfy timing restrictions corresponding to the result of the (b) step, the timing restrictions being given to the plurality of macro blocks.
Further in this case, the (c) step includes performing, after performing the register transfer level design, the circuit design and the layout design on the inside portions as a specific performing, performing a second timing analysis whether the plurality of macro blocks satisfy the timing restrictions based on the result of the specific performing, and performing one of the register transfer level design, the circuit design and the layout design on the inside portions again, when the timing restrictions are not satisfied as the result of the second timing analysis.
In this case, an LSI design method further includes (d) determining a function specification of an LSI, (e) dividing the LSI into the plurality of macro blocks based on the function specification, and (f) determining a size and a shape of each of the plurality of macro blocks to perform a floor plan on an entire portion of the LSI, and wherein the (d), (e), and (f) steps are performed before the (a) step is performed.
Also in this case, when a predetermined timing restriction is not satisfied as the result of the (b) step, at least one of the (d), (e) and (f) steps is performed again.
Further in this case, at least one of the plurality of the macro blocks is a macro block, as a post-designed macro block, of which a design is performed, and the (c) step includes designing the inside portion of one other than the post-designed macro block of the plurality of macro blocks.
In order to achieve another aspect of the present invention, an LSI design method, includes (g) performing a function specification design of an LSI, (h) performing an arrangement wiring on a plurality of macro blocks for the LSI based on the result of (g) step, (i) performing a timing analysis on the plurality of macro blocks based on the result of (h) step, (j) performing a design and a wiring on an inside portion of each of the plurality of macro blocks based on the result of (i) step, (k) performing a arrangement on the plurality of macro blocks for the LSI without performing a wiring on the plurality of macro blocks based on the result of (g) step, (l) performing a design on an inside portion of each of the plurality of macro blocks, (m) performing a first wiring between the plurality of macro blocks and a second wiring on the inside portion of each of the plurality of macro blocks after the (k) and (l) steps are performed, wherein the first and second wirings are performed at a same time to each other, and (n) performing a timing analysis on the plurality of macro blocks after the (m) step is performed, and wherein a first LSI design process includes the (h), (i) and (j) steps and a second LSI design process includes the (k), (l), (m) and (n) steps, and one of the first and second design processes is performed selectively.
In this case, the first design process is performed selectively when the LSI is a LSI in which a timing required is more critical than a predetermined value as the result of the (g) step.
Also in this case, the first design process is performed selectively when a circuit size of the LSI is larger than a predetermined size, as the result of the (g) step.
Further in this case, the second design process is performed selectively when a layout density of the LSI is larger than a predetermined density, as the result of the (g) step.
In order achieve still another aspect of the present invention, an LSI design method, includes (o) performing a floor plan on a plurality of macro blocks for an LSI, (p) performing an arrangement on the plurality of macro blocks, (q) performing a wiring on the plurality of macro blocks, (r) performing a timing analysis on the plurality of macro blocks based on the result of the (q) step to perform a design and a wiring on an inside portion of each of the plurality of macro blocks based on the timing analysis when the wiring as the result of the (q) step fits into a predetermined chip size, and (s) removing the wiring as the result of the (q) step and performing a first wiring between the plurality of macro blocks and a second wiring on the inside portion of each of the plurality of macro blocks, wherein the first and second wirings are performed at a same time after performing a design of the inside portion of each of the plurality of macro blocks when the wiring as the result of the (q) step does not fit into the predetermined chip size.
In order achieve yet still another aspect of the present invention, an LSI design apparatus, includes a first section performing an arrangement wiring on a plurality of macro blocks, a second section performing a timing analysis on the plurality of macro blocks based on the result of the arrangement wiring, and a third section designing an inside portion of each of the plurality of macro blocks based on the result of the timing analysis.
In this case, the second section performs the timing analysis in consideration of a wiring capacitance and a wiring resistor corresponding to the result of the arrangement wiring.
Also in this case, the third section performs a register transfer level design, a circuit design and a layout design on the inside portions such that the plurality of macro blocks satisfy timing restrictions corresponding to the result of the timing analysis, the timing restrictions being given to the plurality of macro blocks.
Further in this case, the third section performs, after performing the register transfer level design, the circuit design and the layout design on the inside portions as a specific performing, a second timing analysis whether the plurality of macro blocks satisfy the timing restrictions based on the result of the specific performing, and performs one of the register transfer level design, the circuit design and the layout design on the inside portions again, when the timing restrictions are not satisfied as the result of the second timing analysis.
In this case, an LSI design apparatus, further includes a fourth section determines a function specification of an LSI, a fifth section divides the LSI into the plurality of macro blocks based on the function specification, and a sixth section determining a size and a shape of each of the plurality of macro blocks to perform a floor plan on an entire portion of the LSI, and wherein the operations of the fourth, fifth, and sixth sections are performed before the operation of the first section is performed.
Also in this case, when a predetermined timing restriction is not satisfied as the result of the operation of the second section, at least one of the operations of the fourth, fifth and sixth sections is performed again.
Further in this case, at least one of the plurality of the macro blocks is a macro block, as a post-designed macro block, of which a design is performed, and the third section designs the inside portion of one other than the post-designed macro block of the plurality of macro blocks.
In order to achieve another aspect of the present invention, an LSI design apparatus, includes a first unit performing a function specification design of an LSI, a second unit performing an arrangement wiring on a plurality of macro blocks for the LSI based on the result of the operation of the first unit, a third unit performing a timing analysis on the plurality of macro blocks based on the result of the operation of the second unit, a fourth unit performing a design and a wiring on an inside portion of each of the plurality of macro blocks based on the result of the operation of the third unit, a fifth unit performing a arrangement on the plurality of macro blocks for the LSI without performing a wiring on the plurality of macro blocks based on the result of the operation of the first unit, a sixth unit performing a design on an inside portion of each of the plurality of macro blocks, a seventh unit performing a first wiring between the plurality of macro blocks and a second wiring on the inside portion of each of the plurality of macro blocks after the operations of the fifth and sixth units are performed, wherein the first and second wirings are performed at a same time to each other, and a eighth unit performing a timing analysis on the plurality of macro blocks after the operation of the seventh unit is performed, and wherein a first LSI design process unit includes the second, third and fourth units and a second LSI design process unit includes the fifth, sixth, seventh and eighth units, and one of the first and second design process units performs selectively.
In order to achieve still another aspect of the present invention, an LSI design apparatus, includes a floor plan unit performing a floor plan on a plurality of macro blocks for an LSI, a arrangement unit performing an arrangement on the plurality of macro blocks, a wiring unit performing a wiring on the plurality of macro blocks, a timing analysis unit performing a timing analysis on the plurality of macro blocks based on the wiring to perform a design and a wiring on an inside portion of each of the plurality of macro blocks based on the timing analysis when the wiring fits into a predetermined chip size, and a removing unit removing the wiring and performing a first wiring between the plurality of macro blocks and a second wiring on the inside portion of each of the plurality of macro blocks, wherein the first and second wirings are performed at a same time after performing a design of the inside portion of each of the plurality of macro blocks when the wiring does not fit into the predetermined chip size.
In order to achieve yet still another aspect of the present invention, a computer readable recording medium for recording a program for a process, includes (t) performing an arrangement wiring on a plurality of macro blocks, (u) performing a timing analysis on the plurality of macro blocks based on the result of the arrangement wiring, and (v) designing an inside portion of each of the plurality of macro blocks based on the result of the timing analysis.
An LSI design method in the present invention, in an LSI design method including a plurality of macro blocks, comprises: a step of performing an arrangement wiring on a plurality of macro blocks; a step of performing a timing analysis between the plurality of macro blocks based on the result of the arrangement wiring; and a step of designing the inside of the macro block based on the result of the timing analysis.
Another LSI design method in the present invention, in an LSI design method including a plurality of macro blocks, selects between a first LSI design method includes: a step of performing an arrangement wiring on a plurality of macro blocks; a step of performing a timing analysis between the plurality of macro blocks based on the result of the arrangement wiring; and a step of wiring the inside of the macro block based on the result of the timing analysis, and a second LSI design method includes: a step of performing only an arrangement without wiring a plurality of macro blocks; a step of designing the inside of the macro block; a step of performing only arrangement on the macro block; a step of designing the inside of the macro block, and a step of simultaneously performing the wiring between the macro blocks and the wiring within the macro block after the above-mentioned steps; and a step of performing a timing analysis after the wiring step, based on a function specification of the LSI.
Still another LSI design method in the present invention, in an LSI design method of performing a layout so that a plurality of macro blocks are mounted in a predetermined chip size, determines a floor plan for each of the plurality of macro blocks, and performs the arrangement between the macro blocks and the wiring between the macro blocks. If the wiring between the macro blocks is accommodated in the predetermined chip size, a timing analysis between the plurality of macro blocks is performed based on the result of the wiring between the macro blocks, and the inner design of the macro block and the inner wiring of the macro block are performed based on the result of the timing analysis. If the wiring between the macro blocks is not accommodated in the predetermined chip size, the wiring between the blocks is stripped off. Then, the wiring between the macro blocks and the inner wiring of the macro block are simultaneously performed after the completion of the inner design of the macro block.